1. Field of the Invention
Embodiments of the present invention generally relate to the fabrication of integrated circuits. More particularly, embodiments of the present invention relate to methods for forming a dielectric barrier film used in manufacturing semiconductor devices.
2. Description of the Related Art
Integrated circuit geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. Today's fabrication facilities are routinely producing devices having 0.1 μm feature sizes, and tomorrow's facilities soon will be producing devices having even smaller feature sizes.
The continued reduction in device geometries has generated a demand for films having low dielectric constant (k) values because the capacitive coupling between adjacent metal lines must be reduced to further reduce the size of devices on integrated circuits. In particular, insulators having dielectric constants, less than about 3.0, are desirable. Examples of insulators having low dielectric constants include spin-on glass, porous film, carbon-doped silicon oxide, and polytetrafluoroethylene (PTFE), which are all commercially available.
However, low k dielectric materials are often susceptible to interlayer diffusion of conductive materials, such as copper, which can result in the formation of short circuits and device failure. A dielectric barrier/liner material is often disposed between metal structure and surrounding low k dielectric materials to prevent interlayer diffusion of metal and byproducts. However, traditional dielectric barrier materials, such as silicon nitride, often have high dielectric constants of 7 or higher. The combination of such a high k dielectric material with surrounding low k dielectric materials results in dielectric stacks having a higher than desired dielectric constant.
Porosity has been introduced to barrier layers, for example by adding methyl g compounds or oxygen doping, to reduce dielectric constant. However, conventional approaches for introducing porosity to barrier layers usually result in loss in etch selectivity and barrier property.
Therefore, there is a need for a method for generating a low k dielectric barrier layers without sacrificing barrier performance and etching resistance.